Performance-Optimal Clustering with Retiming for Sequential Circuits

We propose an exact clustering with retiming algorithm to minimize the clock period for sequential circuits. Without moving ip-ops (FF's) by retiming, conventional clustering algorithms can only handle combina-tional parts and therefore cannot achieve the best cycle time. Pan et al. 2] have proposed an optimal algorithm under the unit gate delay model. We propose a more powerful and faster algorithm that produces optimal results even under the more realistic general gate delay model. Experimental results show that the average ratio of the run time used by Pan's algorithm to ours is 2 : 1. 1 Introduction Circuit clustering groups cells in a design into macros to satisfy some constraints such as area or pin limitations 3]]4]]5]. But this often induces large interconnect delays between macros. Therefore, avoiding performance degradation is a major objective when we perform circuit clustering. Retiming, which repositions ip-ops (FF's) while preserving circuit functionality, can be used to shorten the clock period 1]. Traditional clustering techniques, which do not consider retiming, cannot achieve the optimal performance for sequential circuits 4]]5]. These clustering methods often treat a sequential circuit as combinational parts by dropping all FF's and then clustering each combinational part independently. If we can appropriately relocate FF's by retiming when clustering a circuit, we can achieve better performance. Pan et al. have proposed an approach to combine retiming and clusteringg2]. Under the unit gate delay modell4], their algorithm can achieve the optimal clock period. For the general gate delay model, it can get near-optimal clock period within the maximum delay of any gates in the circuit. They use a labeling technique to achieve the retiming eeect and to integrate it with clustering. Pan's algorithm cannot produce the optimal results under the general delay model because it does not nd the best labeling. If the relocated position for an FF, computed during labeling, is occupied by a gate, the labeling value of this gate has to be modiied.